1. Field of the Disclosure
The present disclosure a wafer level processing method and structure to manufacture a semiconductor chip, the semiconductor chip to be as a backside illumination (BSI) image Sensor Chip.
2. Brief Description of the Related Art
Various methods and systems have been proposed for manufacturing semiconductor chips. For example, an image sensor package and a method for fabricating thereof has been proposed where a substrate having an insulator filled cavity is provided with an image sensor device electrical connected to a metal layer, thereon. A covering plate is then disposed on the substrate. The substrate is subsequently thinned to expose the insulator. Removing a portion of the insulator, a hole is formed and a conductive layer is filled therein to form a via hole. Next, a solder ball is located over a backside of the substrate which is electrically connected to the metal layer through the via hole. The image sensor package is thinned, thus, the dimensions thereof are reduced.
In another example, a crystalline substrate based device has been proposed that includes a crystalline substrate having formed thereon a microstructure, and a transparent packaging layer which is sealed over the microstructure by an adhesive and defines therewith at least one gap between the crystalline substrate and the packaging layer. The microstructure receives light via the transparent packaging layer.
In another example, a wafer level chip size package has been proposed where the package has cavities within which micro-machined parts are free to move, allowing access to electrical contacts, and optimized for device performance. Also a method for fabricating a wafer level chip size package for Microelectromechanical systems (MEMS) devices has been proposed that provides a well packed device with the size much closely to the original one, making it possible to package the whole wafer at the same time and therefore, saves the cost and cycle time.
In another example, a circuit structure has been proposed that includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and second metallic posts have a height of between 20 and 300 microns, with the ratio of the maximum horizontal dimension thereof to the height thereof being less than 4. The distance between the center of the first bump and the center of the second bump is between 10 and 250 microns.